Asynchronous data receiver comprising means for standyby mode switchover

ABSTRACT

A device for receiving asynchronous frames beginning with a header field, the device including a circuit for switching into a stand-by mode, a circuit for recognizing a header field, and a circuit for leaving the stand-by mode when a valid header field is recognized, the stand-by mode including the filtering of at least one signal likely to be emitted by the receiver device during the reception of a header field. The device is suitable in particular for UART circuits that are present in microcontrollers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of devices for transmittingasynchronous data, generally called “UARTs” (Universal AsynchronousReceiver Transceiver) and, more particularly, to the stand-by settingand the activation of an asynchronous data receiver.

2. Description of the Related Art

Asynchronous data are generally transmitted by means of asynchronousframes comprising one or more standard characters. Such standardcharacters generally comprise 10 bits, among which there are 8 data bitspreceded by a start bit and followed with a stop bit. Contrary tosynchronous data transmissions, the receiver does not receive the clocksignal from the emitter, so that the respective clocks of the emitterand the receiver must have, the one in relation to the other, adeviation which does not exceed a certain value in order that the datacan be correctly transmitted.

To aid in better understanding, FIG. 1 shows the format of anasynchronous frame according to protocol LIN (“Local InterconnectNetwork”). This frame first comprises a break character BRK comprising apredetermined number of bits at 0 and a last bit equal to 1 (“extrabit”), then a synchronization character SYNC, and then data charactersCH1, CH2 . . . CHN. Character CH1 can be used as an identification fieldto allow multipoint links between a master device and slave devices.

Character SYNC is represented with more details in FIG. 2 and is equalto [55]h in hexadecimal notation, that is character “10101010” in binarynotation (bits B0 to B7). This synchronization character being precededby a start bit STB at 0 and followed with a stop bit SPB at 1, one hasin total at one's disposal 5 falling edges for matching a local clocksignal to the reference clock signal of character SYNC. The durationbetween the 5 falling edges being equal to 8 times the period T of thereference clock signal. The measure of this duration allows thereference period T to be determined and the period of the local clocksignal to be matched to it.

The first data character CH1 is an identification character whichdefines the attributes of the message formed by the data characters CH2,. . . CHN. The four first bits of this identification character containthe identification of the addressee of the message, the two followingbits indicate the length of the message, and the two last bits areparity bits.

The combination of the break character BRK, the synchronizationcharacter SYNC, and the identification character CH1 constitutes theheader field of a LIN frame.

FIG. 3 schematically shows the architecture of a circuit UART providedfor receiving such asynchronous frames.

A local clock signal CK is delivered by a divider DIV1, generally adivider by 16, receiving a sampling signal CKS as an input. Signal CKSis itself delivered by a programmable divider DIV2 receiving a primaryclock signal CK0 as an input. The ratio between the frequency of signalCK0 and the frequency of signal CKS is determined by a value DVAL loadedin a register DREG of the programmable divider.

Circuit UART further comprises a buffer circuit BUFC and a state machineSM which identifies the break BRK and synchronization SYNC characters,and delivers information signals IS to the outside environment. It willbe considered in the following, by way of a non limiting example, thatthe “outside environment” is the central processing unit of amicrocontroller (not shown) in which circuit UART is arranged. SignalsIS indicate for example that a character SYNC is being received, that areceived data is available for read in circuit BUFC, etc.

Buffer circuit BUFC comprises here two reception registers SREG1, SREG2,an emission register SREG3, a 4 bits counter CT1 (counter by 16), twologic comparators CP1, CP2 and a circuit AVCC. Register SREG1 is a shiftregister of 10 bits, the input SHIFT of which is clocked by signal CKS.It receives data RDT on a serial input SIN connected to a data receptionterminal RPD, and delivers sampled data SRDT (bits b0 to b9) on aparallel output POUT. The data SRDT are applied to the input of circuitAVCC, the output of which delivers a bit Bi which is sent to a serialinput SIN of register SREG2. Each bit Bi delivered by circuit AVCC isconventionally equal to the majority value of the samples of rank 7, 8and 9 (bits b7 to b9) present in register SREG1.

The data SRDT are also applied to an input of comparator CP1, the otherinput of which receives a reference number “1110000000”, forming afalling edge detection criteria. Comparator CP1 delivers a signal FEDETwhich is communicated to the outside environment and which is alsoapplied to a resetting to 6 input (input “SET 6”) of counter CT1, whichis clocked by signal CKS. Counter CT1 delivers a sample counting signalSCOUNT which is applied to an input of comparator CP2, the other inputof which receives, in a binary form, a reference number equal to 9 inbase 10. The output of comparator CP2 drivers the shift input SHIFT ofregister SREG2. Lastly, register SREG3 is a shift register clocked bylocal clock signal CK, receiving data XDT on a parallel input PIN anddelivering serial data XDT on an output SOUT connected to a terminalXPD.

After the reception of character SYNC, the data present in charactersCH1, CH2 . . . are received bit by bit, a data bit Bi delivered bycircuit AVCC (majority value of samples b7 to b9) being loaded intoregister SREG2 every 16 cycles of signal CKS, that is every cycle oflocal clock signal CK. The loading of a bit Bi is performed at the tenthcounting cycle of counter CT1, when the output of comparator CP2 passesto 1. The received data RDT are stored in register SREG2 by groups of 8bits B0-B7 and can be read by means of a parallel output POUT of thisregister.

Character SYNC represented in FIG. 2 allows circuit UART to determinethe value DVAL to be placed into divider DIV2 for obtaining a smalldeviation of the local clock signal CK. This value is such that theperiod Ts of the sampling signal CKS must be equal toTs=D/(8*16)D being the duration measured between the five falling edges of thesynchronization character, that is eight periods T of the referenceclock. The calculation of DVAL may be ensured by a particular wiredlogic circuit (not shown) associated to state machine SM, or by amicrocontroller's central processing unit.

It appears in practice that circuit UART delivers to the outsideenvironment various signals and various data when a message is beingreceived, and that the outside environment performs various operations,in particular reading operations, which are not useful if the message isnot intended to it.

BRIEF SUMMARY OF THE INVENTION

The disclosed embodiments of the present invention release the outsideenvironment from useless tasks, avoiding characters that are notintended to it.

To that effect, the disclosed embodiments of the present inventionprovide a device for receiving asynchronous frames beginning with aheader field, which includes means for switching into a stand-by mode,the stand-by mode including the filtering of at least one signal likelyto be emitted by the receiver device during the reception of a headerfield, means for recognizing a header field, and means for leaving thestand-by mode when a valid header field is recognized.

According to an embodiment, the means for recognizing a header field arearranged to recognize a valid header field when the header fieldcomprises a break character formed of bits having all the same value.

According to an embodiment, the means for recognizing a header field arearranged to recognize a valid header field when the header fieldcomprises a synchronization character.

According to an embodiment, the means for recognizing a header field arearranged to recognize a valid header field when the header fieldcomprises an identification character.

According to an embodiment, the means for recognizing a header field arearranged to recognize a valid header field when the header fieldcomprises an identification character corresponding to an identity ofthe device.

According to an embodiment, the stand-by mode is controlled by a flagwhich can be forced to a predetermined value from the outside of thedevice.

According to an embodiment, the means for recognizing a header field andthe means for leaving the stand-by mode when a valid header field isrecognized comprise a state machine.

The present invention also relates to an integrated circuit comprising adevice according to the invention.

The present invention also relates to a microcontroller comprising adevice according to the invention.

The disclosed embodiments of the present invention also relate to amethod of receiving asynchronous frames beginning with a header field,implemented by means of a frame receiver device comprising a stand-bymode controlled by a predetermined means, the stand-by mode comprisingthe filtering of at least one signal likely to be emitted by thereceiver device during the reception of a header field, and comprising astep of recognizing a header field and an action on the means forcontrolling the stand-by mode when a header field is recognized, so asto let the receiver device leave the stand-by mode if this one is in thestand-by mode.

According to an embodiment, the means for controlling the stand-by modecomprises a flag and the action on the means for controlling thestand-by mode comprises the fact to force the flag to a predeterminedvalue.

According to an embodiment, a header field is recognized as being validwhen it comprises a break character formed of bits having all the samevalue.

According to an embodiment, a header field is recognized as being validwhen it comprises a synchronization character.

According to an embodiment, a header field is recognized as being validwhen it comprises an identification character.

According to an embodiment, a header field is recognized as being validwhen it comprises an identification character which corresponds to anidentity of the device.

According to an embodiment, the steps of recognizing a header field andthe action on the means for controlling the stand-by mode when a headerfield is recognized, are performed by means of a state machine.

In accordance with another embodiment of the invention, amicrocontroller is provided. The microcontroller includes a memorycircuit; a controller coupled to the memory circuit; a uniformasynchronous receiver-transceiver device coupled to the controller andto an input and an output of thee microcontroller. The device includes astate machine configured to send a data-received signal to thecontroller when the device receives data that is available for readingby the controller, the state machine configured to filter thedata-received signal when in a stand-by mode; a circuit for recognizingreception of a header field; and a circuit for leaving the stand-by modewhen a valid header field is recognized.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

These characteristics and advantages as well as others of the presentinvention will be described with more details in the followingdescription of an example of embodiment of a device UART according tothe invention, done in a non limiting way, in conjunction with theaccompanying drawings in which:

FIG. 1, previously described, shows an asynchronous frame according toprotocol LIN,

FIG. 2, previously described, shows a synchronization character,

FIG. 3, previously described, shows a conventional circuit UART,

FIG. 4 shows a microcontroller comprising a circuit UART1 according tothe present invention, and

FIG. 5 shows a state machine according to the present invention in thecircuit UART1 of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 4 schematically shows a microcontroller MC comprising, on a samesilicon chip, a central processing unit UC, a program memory MEM, and acircuit UART1 according to the invention. The circuit UART1 is connectedto input/output pads RPD/XPD of the integrated circuit.

The overall architecture of circuit UART1 corresponds to the one of theconventional UART circuit described in the preamble in relation withFIG. 3, and will not be again described. The central processing unit UCuses circuit UART1 for emitting and receiving asynchronous data via padsXPD, RPD. Circuit UART1 sends, to the central processing unit, a signalDRC (“Data Received”) when data RDT are received and are available forreading in its reception register (register SREG2, FIG. 3), the signalDRC being for example applied to an interruption decoder of the centralprocessing unit. Signal DRC is one of the information signals ISdelivered by circuit UART1 towards the outside environment (signal DRConly being shown in FIG. 4).

Circuit UART1 distinguishes from conventional circuit UART by the factthat it comprises a state machine SM1 provided for managing a stand-bymode in which signal DRC at least is not emitted. The stand-by mode ishere controlled by a stand-by setting flag WU equal for example to 1 inthe stand-by mode and to 0 in the active mode. Flag WU is stored in apredetermined register of circuit UART1, and can be forced to 1 by thecentral processing unit UC in order to set circuit UART1 into thestand-by mode.

Still according to the invention, circuit UART1 leaves the stand-by modeonly when it has detected a valid frame beginning, in a way which willbe described now in relation to protocol LIN by way of a non limitingexample.

In a LIN frame of the type described in the preamble, the breakcharacter BRK consists in a series of 13 bits at 0 clocked by areference clock signal. To take into account of an offset between thissignal and the local clock signal, the detection of this character isperformed by identifying at least 11 bits at 0. This number of 11 bitsis chosen by convention in order to allow a clock deviation of the orderof ±15%.

The state machine SM1 of circuit UART1 comprises thus a first module FWMforming a detection unit of the break character BRK.

An example of embodiment of module FWM of state machine SM1 isrepresented in FIG. 5. The reception of a bit BS at 1 (bit BS precedinga character BRK, Cf. FIG. 1) causes the passage from a waiting stateIDLE to an intermediate state ES. The reception of the following bit B0,depending on Whether it is equal to 0, respectively to 1, causes thepassage to an intermediate state E0 or, respectively, the return tostate IDLE. In state B0, the reception of the second bit B1 followingbit BS, depending on whether it is equal to 0, respectively to 1, causesthe passage to an intermediate state E1 or, respectively, the return tostate IDLE.

By way of generalization, the reception, by the state machine being inan intermediate state Ei, of the (i+1)^(th) bit following bit BS causesthe passage to a state Ei+1 or the return to state IDLE depending onwhether the received bit is equal to 0 or 1.

When index i is equal to 9, the reception of the eleventh bit B10following bit BS, depending on whether it is equal to 0 or 1, causes thepassage to a state E10 or the return to the waiting state.

It should be noted that the break character BRK can be detected in anyother way, for example by means of a shift register of 11 bits, all thebits of which are subject to a logic AND operation.

When the break character BRK is detected, the next characters of theframe are all standard characters formed of 10 bits. These standardcharacters are processed by means of a processing unit which is forexample a second module SWM of state machine SM1.

An example of embodiment of module SWM is also represented in FIG. 5 andcomprises first a state TIME in which the synchronization character SYNCis received and analyzed. As a matter of fact, the structure of theframe is such that the synchronization character SYNC followsimmediately the break character BRK. The end of the synchronizationcharacter SYNC, detected by means of stop bit SPB, causes the passage toa state IDENT, while an error in the recognition of this charactercauses the return to the waiting state IDLE.

In state IDENT, the next character, that is the first identificationcharacter CH1, is received and analyzed. Furthermore, the value of thestand-by setting flag WU is possibly modified.

It is supposed here that the central processing unit has set circuitUART into the stand-by state (WU=1) before the reception of the frame,so that signal DRC (FIG. 4) has not been emitted during the reception ofthe first two characters, the stand-by setting flag WU being equal to 1.

If the identification character CH1 does not correspond to the identityID of circuit UART1, the stand-by setting flag WU is set to 1 whateverits current value may be, and the state machine returns to the waitingstate IDLE. In an alternative embodiment, the stand-by setting flag WUcan be let to its current value (which may be 0 or 1 depending on thevalue set by the outside environment) when the state machine returns tothe waiting state IDLE.

If, on the other hand, the identification character CH1 indeedcorresponds to the identity ID of circuit UART1, the stand-by settingflag WU is set to 0, which corresponds to the “wake-up” of circuit UART1in relation to the outside environment and the passage of state machineSM1 to a state “DATA”.

In state DATA, the data standard characters are processed consecutivelyin a known manner. When a standard character is received, signal DRC isemitted in order to cause an interruption in the central processing unitand the sending, by the latter, of the received data to a readsubroutine.

The number of these characters being variable, there is provided alength indicator EOD which is equal to 1 as long as a new character mustfollow and equal to 0 when the currently processed character is the lastof the frame. When this indicator is equal to 1, it causes the return tostate DATA. On the contrary, when it is equal to 0, it causes thepassage to state IDLE.

The management of the stand-by mode of some circuit being per se anoperation within the skills of those skilled in the art, it does notneed to be specifically developed. In the stand-by mode, circuit UART1preferably filters all the characters which do not correspond to thewake-up sequence, that is the frame header field provided with characterCH1. On the other hand, when the wake-up sequence is recognized, thecentral processing unit UC is informed, for example by means of aninterruption caused by signal DRC.

Of course, the stand-by mode described above can be superposed toanother mode of the same type which would be further provided.

The present invention is of course likely to have various alternativesand embodiments. In particular, any step or any means described abovecan be replaced with an equivalent step or an equivalent means withinthe scope and spirit of the present invention.

Furthermore, although there has been proposed above to leave thestand-by mode when the state machine SM of circuit UART1 has checkedthat the identification character CH1 indeed corresponds to a predefinedidentity ID, this checking operation can also be performed by thecentral processing unit. In this case, circuit UART1 leaves the stand-bymode when a valid identification character CHI is received, withoutchecking its content, and emits signal DRC. After reception of signalDRC, reading of character CH1 in circuit UART1 (register SREG2, FIG. 3)and checking of character CH1, the central processing unit UC forcesagain circuit UART1 into the stand-by mode, setting flag WU to 11 ifcharacter CH1 does not correspond to identity ID, and otherwise waitsfor the next signal DRC for reading the next character CH2.

All of the above U.S. patents, U.S. patent application publications,U.S. patent applications, foreign patents, foreign patent applicationsand non-patent publications referred to in this specification and/orlisted in the Application Data Sheet, are incorporated herein byreference, in their entirety.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A device (UART1) for receiving asynchronous frames beginning with aheader field, comprising: means for switching into a stand-by mode, thestand-by mode comprising the filtering of at least one signal likely tobe emitted by the receiver device during the reception of a headerfield, means for recognizing the header field, and means for leaving thestand-by mode when a valid header field is recognized.
 2. The device ofclaim 1, wherein the means for recognizing a header field are arrangedto recognize a valid header field when the header field comprises abreak character formed of bits having all the same value.
 3. The deviceof claim 1, wherein the means for recognizing a header field arearranged to recognize a valid header field when the header fieldcomprises a synchronization.
 4. The device of claim 1, wherein the meansfor recognizing a header field are arranged to recognize a valid headerfield when the header field comprises an identification characters. 5.The device of claim 1 wherein the means for recognizing a header fieldare arranged to recognize a valid header field when the header fieldcomprises an identification character corresponding to an identity ofthe device.
 6. The device of claim 1, wherein the stand-by mode iscontrolled by a flag that can be forced to a predetermined value fromoutside of the device.
 7. The device of claim 1, wherein the means forrecognizing a header field and the means for leaving the stand-by modewhen a valid header field is recognized comprise a state machine.
 8. Anintegrated circuit, comprising a device according to claim
 1. 9. Amicrocontroller, comprising a device according to claim
 1. 10. A methodof receiving asynchronous frames beginning with a header field, themethod implemented by means of a frame receiver device having a stand-bymode controlled by a predetermined means, the stand-by mode involvingthe filtering of at least one signal likely to be emitted by thereceiver device during the reception of a header field, the methodcomprising: a step of recognizing a header field and of an action on themeans for controlling the stand-by mode when a header field isrecognized, so as to let the receiver device leave the stand-by modewhen it is in the stand-by mode.
 11. The method of claim 10, wherein themeans for controlling the stand-by mode comprise a flag and the actionon the means for controlling the stand-by mode comprises forcing theflag to a predetermined value.
 12. The method of claim 10, wherein aheader field is recognized as valid when it comprises a break characterformed of bits having all the same value.
 13. The method of claim 10,wherein a header field is recognized as valid when it comprises asynchronization character.
 14. The method of claim 10, wherein a headerfield is recognized as valid when it comprises an identificationcharacter.
 15. The method of claim 10, wherein a header field isrecognized as being when it comprises an identification character thatcorresponds to an identity of the device.
 16. The method of claim 10wherein the steps of recognizing a header field and of the action on themeans for controlling the stand-by mode when a header field isrecognized are performed by means of a state machine.
 17. A device forreceiving asynchronous frames beginning with a header field, the devicecomprising: a circuit for switching into a stand-by mode duringreception of a header field, the stand-by mode structured to filter atleast one signal to be emitted by the device during the reception of theheader field; a circuit for recognizing the header field; and a circuitfor leaving the stand-by mode when a valid header field is recognized.18. A device for receiving asynchronous frames that include a headerfield, the device comprising: a state machine comprising a circuit forrecognizing a header field received by the device, a circuit forswitching into a stand-by mode for filtering of at least one signallikely to be emitted by the device during the reception of the headerfield, and a circuit for leaving the stand-by mode when a valid headerfield is recognized.
 19. An integrated microcontroller, comprising: amemory circuit; a controller coupled to the memory circuit; a uniformasynchronous receiver-transceiver device coupled to the controller andto an input and an output of the microcontroller, the device comprising:a state machine configured to send a data-received signal to thecontroller when the device receives data that is available for readingby the controller, the state machine configured to filter thedata-received signal when in a stand-by mode; a circuit for recognizingreception of a header field; and a circuit for sending a control signalto the state machine to enter the stand-by mode when a valid headerfield is not recognized and to leave the stand-by mode when a validheader field is recognized.
 20. The microcontroller of claim 19, whereinthe state machine is configured to not filter the data-received signalwhen the circuit for leaving the stand-by mode recognizes a valid headerfield.
 21. The circuit of claim 20, wherein the device further comprisesa register for storing a flag having a predetermined value to initiatethe stand-by mode.
 22. The circuit of claim 21, wherein the controlleris configured to force the flag to initiate the stand-by mode of thedevice.
 23. The microcontroller of claim 22 wherein the device isconfigured to detect an error in recognizing the header field and tocause the device to remain in the stand-by mode.